Corporate Headquarters. Cypress Semiconductor Corp. 198 Champion Court San Jose, CA 95134 USA Tel: +1-408-943-2600. The Questa Verification IP Serial family enables fast and accurate verification of designs that use the following protocols: I2C, JTAG, SPI, UART, I2S, Smart Card, and SPI.
Mentor, a Siemens business, is pleased to announce the availability of ModelSim 2019.2, is unified debug and simulation environment gives today’s FPGA designers advanced capabilities in a productive work environment.
Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused.
In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSimâs award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.
The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
Product: Mentor Graphics Xpedition Enterprise Version: VX.2.1 with Documentation and Library Supported Architectures: 32bit / 64bit Website Home Page :
Language: english System Requirements: PC Supported Operating Systems: Windows Server 2008 / Windows Server 2012 / Windows 7even or above Size: 9.4 Gb
Mentor Graphics Corporation announced the first update of the new Xpedition printed circuit design (PCB) flow to address the increasing complexity of todayâs advanced systems designs. The increasing densities of electronics products are forcing companies to develop highly compact system designs with more functionality, and at lower costs. To efficiently manage the density and performance requirements for advanced PCB systems, the new Xpedition flow provides advanced technologies to enable design and verification of 3D rigid-flex structures, and to automate layout of high-speed topologies with advanced constraints.
Managing Advanced Rigid Flex Design Complexity
Flex and rigid-flex PCBs are now found in all types of electronics products, from small consumer devices to aerospace, defense and automotive electronics where high reliability and safety are critical. The Xpedition rigid-flex technology enables a streamlined design process from initial stack-up creation through manufacturing.
Engineers can design complex rigid and flex PCBs in a fully supported 3D environment (3D design and verificationânot just a 3D view), resulting in a correct-by-construction methodology for optimum reliability and product quality. 3D verification ensures that bends are in the right position, and elements on the board do not interfere with folding; this can be reviewed early in the design stage to prevent costly redesigns. Users can then export a 3D solid model to MCAD for efficient bi-directional PCB-enclosure co-design.
Integration with Mentorâs leading HyperLynx high-speed analysis technology enables optimization of signal and power integrity across complex rigid-flex stack-up structures. For fabrication preparation, the Xpedition flow provides all flex and rigid information using the ODB++ common data format. This methodology eliminates data ambiguities by clearly communicating the finished board intent to the fabricator. The new Xpedition flow is the optimum solution designed specifically for flex and rigid-flex design, from conception through fabrication output.
For efficient rigid-flex development, key features and capabilities include:
â Definition of the rigid-flex stack-up with unique outlines for each region, enabling simpler design changes than stack-up by zone. Standard flex materials (e.g. laminates, âembeddedâ or âbikiniâ cover layers, stiffeners, adhesives, etc.) can be included in the stack-up. â Full support of flex bends to manage where and how the PCB bends, including parts placement on flex layers, flex routing, plane shape fills, tear drops and trace drops. Once bends are defined, the design can be viewed and validated in 3D to ensure there are no collisions. â Powerful user interface with intuitive and simple selection controls to properly manage the design. â Electrical rule checking (ERC) using a customizable local rules checker and a comprehensive set of post-design checks for first-pass success. â Flex-aware signal and power integrity analysis, enabling accurate modeling of interconnect as it passes through different stack-up regions. â Design for manufacturing (DFM) validation and new product introduction (NPI) tools to ensure seamless PCB design to fabrication management and efficiency.
Automated Layout for High-Speed Designs
The new Xpedition release also features advanced layout automation to address increasing complexity in high-speed designs and emerging guidelines for high-end computing chip-sets. The following key functionality helps optimize designs for performance:
â Tabbed routing, an interconnect geometry used to minimize crosstalk and impedance discontinuities, can be created and modified on high-speed traces. â Designers can create and modify a routing strategy with sketch plans that define a path for trunks of nets, including trace shielding. â Enhanced tuning enables better feedback and control during interactive editing to achieve high-speed constraints. â Nets which require back drilling can be defined in layout and output for manufacturing. â Engineers can import Polar stack-ups and layer mapping directly into the constraint manager to simplify design start-up. â A new user interface enables review of all design rule checks in the design for quick identification and resolution of electrical and manufacturing design violations.
About Mentor Graphics
Mentor Graphics is a technology leader in electronic design automation (EDA), providing software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. The company offers innovative products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design. Mentor Graphics has the broadest industry portfolio of best-in-class products and is the only EDA company with an embedded software solution.